1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to a liquid crystal display device and a method of fabricating a liquid crystal display device.
2. Discussion of the Related Art
Advancements within information communication fields have increased the demand for various types of display devices. In response to this demand, various flat panel display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, electro-luminescent display (ELD) devices, and vacuum fluorescent display (VFD) devices, have been developed to replace conventional cathode ray tube (CRT) devices. In particular, the LCD devices are commonly used because of their high resolution, light weight, thin profile, and low power consumption. In addition, the LCD devices have been implemented in mobile devices, such as monitors for notebook computers, and have been developed for monitors of computers and televisions. Accordingly, efforts to improve image quality of LCD devices have contrasted with the benefits of high resolution, light weight, thin profile, and low power consumption. In order to incorporate the LCD devices in general image display devices, image quality, such as fineness, brightness, and large-size, must be realized.
In general, the LCD device includes an LCD panel for displaying an image thereupon, and a driving part for supplying a driving signal to the LCD panel. The LCD panel includes lower and upper substrates bonded together having a fixed interval therebetween, and a liquid crystal material layer that is injected between the lower and upper substrates. The lower substrate (i.e., TFT array substrate) includes a plurality of gate lines arranged along a first direction spaced apart by fixed intervals, a plurality of data lines arranged along a second direction perpendicular to the first direction spaced apart by fixed intervals to define a plurality of pixel regions, a plurality of pixel electrodes within each of the pixel regions defined by crossings of the plurality of gate and data lines, and a plurality of thin film transistors that are individually enabled according to a signal supplied by the gate line for transmitting a signal supplied by the data line to the pixel electrode. The upper substrate (i.e., color filter substrate) includes a black matrix film provided on regions of the second substrate for preventing light leakage, except within the pixel regions of the first substrate, and R/G/B color filter layers for displaying colors, and a common electrode, which together with the pixel electrode, display image data.
During a fabrication process, a predetermined interval is maintained between the lower and upper substrates using spacers to define a cell gap, and the lower and upper substrates are bonded to each other by a sealant material provided along a periphery of the first and second substrates. Then, liquid crystal material is injected into the cell gap formed between the lower and upper substrates through an inlet port of the sealant material. As a result of the fabrication process, a plurality of LCD panels are formed on one substrate according to overall sizes of the substrates and the LCD panel.
FIG. 1 is a plan view of a pixel region of an array substrate according to the related art. In FIG. 1, a plurality of gate lines 11 are formed on a transparent substrate at fixed intervals, a gate electrode 11b is formed to extend from each of the gate lines 11, a storage lower electrode is formed adjacent to one of the gate lines, and a gate pad 11a is formed at one end of each of the gate lines 11. In addition, a gate insulating layer (not shown) is formed on the transparent substrate including the gate line 11, the gate electrode 11b, and the storage lower electrode, and an active layer 13 is formed on the gate insulating layer above the gate electrode 11b, wherein the active layer 13 includes a silicon layer and a doped silicon layer.
Next, a plurality of data lines 14 are formed perpendicular to the gate lines 11, thereby defining a plurality of pixel regions, and a data pad 14a is formed at one end of each of the data lines 14. In addition, a source electrode 14b is formed to extend from each of the data lines 14 to overlap a first side of the active layer 13, a drain electrode 14c is formed apart from the source electrode 14b to overlap a second side of the active layer 13, and a storage upper electrode 14d is formed above the storage upper electrode during formation of the drain electrode 14c. 
Next, a passivation layer (not shown) is formed on an entire surface of the transparent substrate, and includes first and second contact holes 16a and 16b corresponding to the storage upper electrode 14d and the drain electrode 14c, respectively, and third and fourth contact holes 17a and 17b corresponding to the gate pad 11a and the data pad 14a, respectively. The passivation layer is formed of one material of an organic insulating group containing Benzocyclobutene (BCB) or a photoacrylic resin. A pixel electrode 15 is formed on the pixel region of the passivation layer to connect to the drain electrode 14c and the storage upper electrode 14d through the first and second contact holes 16a and 16b. Then, gate and data pad terminals 18a and 18b are formed on the third and fourth contact holes 17a and 17b, respectively, such that the passivation layer is adjacent to the third and fourth contact holes 17a and 17b. The gate and data pad terminals 18a and 18b are formed of a transparent conductive layer similar to the material used to form the pixel electrode.
FIG. 2 is a cross sectional view along I-I′ of FIG. 1 according to the related art. In FIG. 2, a metal pad 21, such as the gate or data pad, is formed on a predetermined region of the transparent substrate 20, wherein the metal pad 21 is formed of a conductive metal material. Then, an inorganic insulating layer 22 is formed on the transparent substrate 20 including the metal pad 21 using the same material as the gate insulating layer (not shown). In addition, an organic insulating layer 23 is formed on the inorganic insulating layer 22 using the same material as the passivation layer (not shown). Subsequently, the organic insulating layer 23 and the inorganic insulating layer 22 are selectively etched to expose a predetermined region of the metal pad 21, thereby forming a contact hole. A pad terminal 24 is formed on the contact hole such that the organic insulating layer 23 is adjacent to the contact hole. Accordingly, the pad terminal 24 is formed of a transparent conductive oxide (TOC), and the metal pad 21 directly contacts the pad terminal 24.
In FIG. 2, a conductive metal, such as aluminum Al, molybdenum Mo, tungsten W or a conductive metal alloy, is deposited on the transparent substrate 20, and patterned. Accordingly, the gate line (not shown) extends from the metal pad 21, the gate electrode (not shown) protrudes from the gate line, and a storage capacitor region of an adjacent gate line serves as the storage lower electrode.
Next, an insulating material, such as a silicon dioxide SiO2 or a silicon nitride SiNX, is deposited on an entire surface of the transparent substrate 20 including the gate line (not shown) to form an inorganic insulating layer 22. Accordingly, the inorganic insulating layer 22 serves as the gate insulating layer. After that, the organic insulating layer 23 is deposited on the inorganic insulating layer 22 including the metal pad 21. The transparent conductive oxide (TOC) is deposited on the entire surface of the organic insulating layer 23 including the contact hole, and is selectively patterned to form the pad terminal 24 on the contact hole such that the organic insulating layer 23 is adjacent to the contact hole. As a result, the metal pad 21 directly contacts the pad terminal 24.
However, impurities may be deposited on the metal pad 21 when forming the metal pad 21 to directly contact the pad terminal 24. For example, carbon or oxygen elements from the organic insulating layer 23 and fluorine elements from an etching gas may be deposited on the metal pad 21 during the process for forming the contact hole by etching the organic insulating layer 23 to from the contact hole. Accordingly, these elements increase contact resistance.
FIG. 3 is a cross sectional view along I-I′ of FIG. 1 according to the related art. In FIG. 3, a contact line includes a barrier layer 25 formed underneath the pad terminal 24, wherein the barrier layer 25 is formed of the same material as the metal pad 21. In addition, use of the barrier layer 25 may be incorporated into a contact portion between the data pad terminal and the data pad at one end of the data line, a contact portion between the storage upper electrode and the pixel electrode, and a contact portion between the drain electrode and the pixel electrode, as well as a contact portion between the gate pad terminal and the gate pad at one end of the gate line. However, an additional masking process is required to form the barrier layer 25, thereby complicating the fabrication process, and increasing fabrication costs. Similarly, in FIG. 2, impurities from the organic insulating layer and etching gas may be deposited on the metal pad during the process of forming the contact hole, thereby increasing contact resistance and deteriorating picture quality.